The present invention relates to a mounting structure and a method of producing a semiconductor device.
In an assembly by flip chip bonding in which a LSI is directly mounted on an interconnection substrate by metal bumps or the like, there has been generally employed a method of melting-and-bonding the LSI chip with solder bumps mounted thereon to the interconnection substrate by use of reflow heating.
This method is performed mainly for the reason of such advantages on process as the solder is melted at a relatively low temperature and as it is possible to compensate, because of the self-alignment effect, positional deviations caused at the time of mounting the LSI chip.
However, in the case where the interconnection substrate is an organic, plastic substrate, large thermal strain is caused in the solder bumps due to a difference of thermal expansion coefficient between the LSI chip and the interconnection substrate, and there occurs such a fear as fatigue fracture is caused at the solder-bonding portions during a temperature cycle test or the like.
As means for preventing this phenomenon, there has been usually performed a method (, that is, a mounting method generally called as an underfill structure)in which a gap defined between the LSI chip and the interconnection substrate is filled with an epoxy thermosetting resin having fine particles (generally called as a filler) added thereto, to thereby restrain deformation caused due to the difference of thermal expansion between the LSI chip and the interconnection substrate, whereby the thermal strain caused in the solder bumps is reduced and the bonding reliability thereof during the temperature cycle thereof.
However, in the mounting method by use of the underfill structure, there is needed an additional step of filling the gap with the resin after mounting the LSI chip on the interconnection substrate, so that there is caused a problem that a production cost is increased.
In particular, in such a case of mounting a plurality of chips as in a multi-chip module (MCM), the resin-filling process is needed regarding each of the chips, so that a great loss is caused regarding the tact for the mass production thereof as well as the cost.
Accordingly, in recent years, there is noted a mounting method called a flip chip attach method (hereinafter, simply refer to an FCA method) in which the preoduction steps are simplified.
The FCA method is explained below while referring to JP-A-10-270496, the entire contents of which are incorporated herein by reference.
In this publication, there is shown a schematic cross sectional view of a semiconductor device in which bump pads formed on the electrode pads of a LSI chip are made to be in pressure contact with the electrode pads of the interconnection substrate, so that they are electrically connected.
Specifically, each of the bump pads is formed on each of the electrode pads formed on the LSI chip. Next, a film-like adhesive made of a thermosetting resin is temporarily pressure-bonded onto each of the electrode pads formed on the interconnection substrate. Finally, the LSI chip is mounted at a position at which the bump pads on the LSI chip correspond to the electrode pads on the interconnection substrate and is simultaneously contacted therewith under heating-and-pressure, and the resin is cured in a state in which each of the bump pads is in pressure contact with each of the electrode pads of the interconnection substrate.
By the cooling performed from the temperature of the pressure-contact, there occur heat shrinkage and curing shrinkage in the resin, and contact pressure is generated between each of the bump pads and each of the electrode pads formed on the interconnection substrate. Because of the contact pressure, the bump pads are electrically connected to the electrode pads formed on the interconnection substrate.
In the FCA method, since the bump pads and the electrode pads on the interconnection substrate are not bonded by alloying, there does not occur such a phenomenon as large thermal strain is caused on each of the bump pads due to the difference of thermal expansion between the LSI chip and the interconnection substrate.
Accordingly, since no underfill step is needed and since the period of time of the pressure-contact is short, the production cost can be reduced to a low level. In addtion, in the method, it is possible to address the fine-connecting-pitch design expected to proceed rapidly in the future, and it is possible to perform the test under a state of semi-cured state of the resin, so that it becomes easy to perform the testing and repairing of the semiconductor device.
Further, because of so-called xe2x80x9cflux-lessxe2x80x9d and xe2x80x9clead-lessxe2x80x9d achieved in the FCA method, there is an advantage that an influence of alpha rays and an influence on the environment can be reduced.
However, on the other hand, since in the FCA method the bump pads are electrically connected to the electrode pads of the interconnection substrate by the contact pressure, not by alloying, there occurs a problem that the contact pressure is lost within an guaranteed temperature range of the semiconductor device due to the influence of the thermal expansion difference caused between the metal bump pads and the adhesive used to seal them, so that electrical disconnection is caused.
To address the problem mentioned above, it is performed, in the prior arts, to select an adhesive having a proper physical property, which is however preformed only experientially by repeating the trial manufacture or the like.
Thus, in the invention is analyzed, by use of the structural analysis, the respect as to how the contact pressure, which is obtained after the steps of the pressure-contacting and the curing achieved between each of the bump pads formed on the LSI chip and each of the electrode pads formed on the interconnection substrate, is varied due to the variation of various boundary conditions occurring between each of the bump pads and each of the electrode pads. In addition, the inventors of the invention have researched essential respects for obtaining such a structure as to bring about the contact pressure sufficient within the guaranteed temperature range of the semiconductor device. As the results thereof, the inventors of the invention have found out a method for making it possible to address the problem of the prior arts and have realized a semiconductor device having a mounting structure which is capable of addressing the problem of the prior arts.
An object of the present invention is to realize a semiconductor device which can keep with high reliability, within an guaranteed temperature range, the electric connection between each of the bump pads formed on the LSI chip and each of the electrode pads formed on the interconnection substrate, and a manufacturing method thereof.
According to the first to seventh aspects of the present invention, there are provided the following semiconductor devices and methods.
(1) A semiconductor device comprising
at least one LSI chip provided on an electrode pad face thereof with metallic bump pads, and
a multi-layer interconnection substrate having an outermost layer formed of an organic portion which substrate is provided on the organic portion thereof with metallic electrode pads each located in a position corresponding to that of each of said bump pads of the LSI chip,
each of the bump pads of the LSI chip being in pressure contact with each of the electrode pads of the interconnection substrate through an adhesive so that each of the bump electrodes is electrically connected to each of the electrode pads formed in the interconnection substrate,
the adhesive having a thermal expansion coefficient ranging from 20 to 60 ppm when measured by TMA measurement, so that each of the bump pads and each of the electrodes pads formed on the multi-layer interconnection substrate is in electrical contact with each other within an elastic deformation range of each of the bump pads and electrode pads at a cooling lower limit temperature defined within a guaranteed temperature range of the semiconductor device,
the organic portion having at a room temperature circumstance a storage elastic modulus ranging from 5 to 10 GPa when measured by DMA measurement,
said organic portion further having a peak value of a loss coefficient, which peak value is equivalent to a glass transition temperature thereof, in a range of 100xc2x0 C. to 250xc2x0 C. when measured by the DMA measurement and having no peak value of the loss coefficient in another range of 0xc2x0 C. to 100xc2x0 C.
(2) A semiconductor device comprising
at least one LSI chip provided on an electrode pad face thereof with metallic bump pads, and
a multi-layer interconnection substrate having an outermost layer formed of an organic portion which substrate is provided on the organic portion thereof with metallic electrode pads each located in a position corresponding to that of each of the bump pads of the LSI chip,
each of the bump pads of the LSI chip being in pressure contact with each of the electrode pads of the interconnection substrate through an adhesive so that each of the bump electrodes is electrically connected to each of the electrode pads formed in the interconnection substrate,
the adhesive having a thermal expansion coefficient ranging from 20 to 60 ppm when measured by TMA measurement, so that each of the bump pads and each of the electrodes pads formed on the multi-layer interconnection substrate is in electrical contact with each other within an elastic deformation range of each of the bump pads and electrode pads at a cooling lower limit temperature defined within a guaranteed temperature range of the semiconductor device,
the organic portion having at a room temperature circumstance a storage elastic modulus ranging from 5 to 10 GPa when measured by DMA measurement.
(3) A semiconductor device comprising
at least one LSI chip provided on an electrode pad face thereof with metallic bump pads, and
a multi-layer interconnection substrate having an outermost layer formed of an organic portion which substrate is provided on the organic portion thereof with metallic electrode pads each located in a position corresponding to that of each of the bump pads of the LSI chip,
each of the bump pads of said LSI chip being in pressure contact with each of the electrode pads of the interconnection substrate through an adhesive so that each of the bump electrodes is electrically connected to each of the electrode pads formed in the interconnection substrate,
the adhesive having a thermal expansion coefficient ranging from 20 to 60 ppm when measured by TMA measurement, so that each of the bump pads and each of the electrodes pads formed on the multi-layer interconnection substrate is in electrical contact with each other within an elastic deformation range of each of the bump pads and electrode pads at a cooling lower limit temperature defined within a guaranteed temperature range of the semiconductor device,
the organic portion having a peak value of a loss coefficient, which peal value is equivalent to a glass transition temperature thereof, in a range of 100xc2x0 C. to 250xc2x0 C. when measured by the DMA measurement and having no peak value of the loss coefficient in another range of 0xc2x0 C. to 100xc2x0 C.
(4) A semiconductor device comprising
at least one LSI chip provided on an electrode pad face thereof with metallic bump pads, and
a multi-layer interconnection substrate having an outermost layer formed of an organic portion which substrate is provided on the organic portion thereof with metallic electrode pads each located in a position corresponding to that of each of the bump pads of the LSI chip,
each of the bump pads of the LSI chip being in pressure contact with each of the electrode pads of the interconnection substrate through an adhesive so that each of the bump electrodes is electrically connected to each of the electrode pads formed in the interconnection substrate,
the adhesive having a thermal expansion coefficient ranging from 20 to 40 ppm when measured by TMA measurement, so that each of the bump pads and each of the electrodes pads formed on the multi-layer interconnection substrate is in electrical contact with each other within an elastic deformation range of each of said bump pads and electrode pads at a cooling lower limit temperature defined within a guaranteed temperature range of the semiconductor device,
the organic portion having at a room temperature circumstance a storage elastic modulus ranging from 10 to 20 GPa when measured by DMA measurement,
the organic portion further having a peak value of a loss coefficient, which peak value is equivalent to a glass transition temperature thereof, in a range of 100xc2x0 C. to 250xc2x0 C. when measured by the DMA measurement and having no peak value of the loss coefficient in another range of 0xc2x0 C. to 100xc2x0 C. 
(5) A semiconductor device according to any one of the aspect (1) to (4), wherein the organic portion provided as the outermost layer of the multiple-layer interconnection substrate is formed of a build-up portion.
(6) A semiconductor device according to any one of the aspects (1) to (4), wherein the adhesive is an anisotropic conductive material in which conductive particles are mixed.
(7) A method of manufacturing a semiconductor device comprising at least one LSI chip provided on an electrode pad face thereof with metallic bump pads, and a multi-layer interconnection substrate having an outermost layer formed of an organic portion which substrate is provided on the organic portion thereof with metallic electrode pads each located in a position corresponding to that of each of said bump pads of the LSI chip, each of said bump pads of said LSI chip being in pressure contact with each of the electrode pads of the interconnection substrate through an adhesive so that each of the bump electrodes is electrically connected to each of the electrode pads formed in the interconnection substrate, the method comprising the steps of:
preparing the interconnection substrate having the organic portion having at a room temperature circumstance a storage elastic modulus ranging from 5 to 10 GPa when measured by DMA measurement, the organic portion further having a peak value of a loss coefficient, which peak value is equivalent to a glass transition temperature thereof, in a range of 100xc2x0 C. to 250xc2x0 C. when measured by the DMA measurement and having no peak value of said loss coefficient in another range of 0xc2x0 C. to 100xc2x0 C.;
pressure-bonding onto the electrode pads of the interconnection substrate the adhesive having axe2x80x2 thermal expansion coefficient ranging from 20 to 60 ppm when measured by TMA measurement so that each of said bump pads and each of the electrodes pads formed on the multi-layer interconnection substrate is in electrical contact with each other within an elastic deformation range of each of the bump pads and electrode pads at a cooling lower limit temperature defined within a guaranteed temperature range of said semiconductor device; and
thermal-pressure-contacting each of the bump electrodes of the LSI chip and each of the electrode pads of the multi-layer interconnection substrate with each other and the curing the adhesive so that each of the bump electrodes of said LSI chip and each of said electrode pads of the multi-layer interconnection substrate are electrically connected to each other.
In the present specification, the xe2x80x9cthermal pressure contactxe2x80x9d or xe2x80x9cthermal-pressure-contactingxe2x80x9d means contacting under heating and pressure.